Computing devices such as servers may be configured to include multiple processors in separate processor sockets. Each processor may include processor circuitry having one or more processor cores. Also, point-to-point interconnects may communicatively couple processor circuitry resident in one processor socket to neighboring processor circuitry resident in one or more other processor sockets. These point-to-point interconnects may operate according to one or more industry technologies such as the Intel® QuickPath Interconnect (“QPI”) technology or HyperTransport™ Consortium's HyperTransport (“HT”) technology.
In some server configurations, processor circuitry resident in separate processor sockets may allow for non-uniform memory access (NUMA) between their respective caches such as last level caches (LLCs). For example, QPI or HT operated point-to-point interconnects may allow for a second processor circuitry's cache to be accessed by a first processor circuitry. The access to the first processor circuitry's cache may be done in a manner that has less access latency than having the second processor circuitry access non-cache or main memory.
Existing power management solutions for multi-socket server systems may include switching a given processor circuitry's performance or power state (frequency/voltage) to operate at lower power levels when the given processor circuitry is underutilized or has idle processing capacity. For example, a first processor circuitry operating in a first processor socket may be operating at a low power state yet a second processor circuitry operating in a second processor socket may be operating at a higher power state. The second processor circuitry operating at the higher power state may still request access to the first processor circuitry's cache even though the first processor circuitry may be operating at a lower power state.